Sizes of semiconductor structures in advanced integrated circuits are progressively decreasing with technology demands. As a result, a minimum spacing between a contact and a polysilicon control gate in, e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET) is also decreasing. It is known that in such transistors, failures in flash memory (e.g., leakages between word and bit lines in the memory) may be caused by breakdown (e.g., inadequate spacing) between control gates and diffusion contacts. With technology scaling, this breakdown between the control gates and the diffusion contacts is exacerbated, even for logic circuits.
To prevent the breakdown between control gates and diffusion contacts in semiconductor structures, on-chip processing (e.g., lithographic processing) of the control gates and the diffusion contacts may need to be monitored, to fabricate these structures. More specifically, actual spacing between the control gates and the diffusion contacts may need to be electrically-determined. However, no known solution exists to monitor the on-chip processing of the control gates and the diffusion contacts and/or to electrically determine their actual spacing. In addition, due to technology scaling, proper sizing and alignment of the control gates and the diffusion contacts are more difficult to achieve and can no longer be guaranteed.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.